Use cases
Where one gate
beats a thousand.
Each use case below is grounded in a measured result or a property of the released design — not a vision slide. Where the grounding is pending physical validation, we say so.
Education & research kits
A GPU whose entire pipeline a student can read, synthesize, probe, and rebuild — multiplication is literally one AND gate you can point at. From Verilog to VGA glow in a weekend, on a fully open toolchain.
The 68-page build guide exists; the full design fits 30% of a $25–55 FPGA; $80–150 total BOM.
Radiation & harsh-environment compute
Above ~0.5% bit-error rate, stochastic arithmetic degrades gracefully where binary corrupts catastrophically — a single flipped bit is 1/L of an answer, not the MSB. A candidate fabric for CubeSats, high-altitude, and high-EMI industrial settings.
Site-resolved fault injection, N=10,000 with 95% CIs; analytic crossover 0.6% matches simulated ~0.5%.
Minimum-silicon instrument displays
Gauges, medical monitors, and panel displays need smooth gradients, not teraflops. The SC fabric draws banding-free shading at 3-bit color — the dithering is free, by physics — in a corner of the cheapest FPGAs.
White-noise dithering proof + rendered evidence; RGB332 output via a resistor DAC; 2,395 LUT4 cluster.
Voltage-overscaled edge devices
Dropping supply voltage saves energy but causes timing errors binary logic can't survive. SC's bit-level error tolerance is exactly the property voltage-overscaled designs need — trade exactness for the last milliwatts.
Fault-tolerance evidence above; the revised paper names voltage-overscaled accelerators as the matching literature.
Shared graphics + inference fabric
The same compute unit that shades pixels has MAC lanes and a 52-cell tanh — the workhorse ops of small neural networks. One tiny fabric can render the UI and run the wake-word model, time-sliced.
sc_mac (7 cells) and sc_tanh (52 cells) are synthesized, tested RTL in the released design.
Runtime quality-scalable rendering
One register changes L: 68 fps rough preview or 4.5 fps near-exact frame, on identical silicon. For battery-aware wearables and previews, precision becomes a dial, not a redesign.
Cycle-accurate model: 68 / 18 / 4.5 fps at L=256/1024/4096 (320×240), Table V of the revised paper.
And where we'd turn you away
If you need frames per second or joules per op, buy binary.
Our own gate-level measurements say a conventional GPU out-renders and out-efficiencies StochastiCore per operation by large factors — those numbers are on the evidence page at full size. We sell the wave where the wave wins: silicon area, fault grace, free dithering, and a build cost measured in pocket money.