Taraṅga is not a product on a shelf — it is an open hardware research program at the point where backing changes the outcome. StochastiCore is peer-revised, synthesized, and simulated down to the LFSR; the one thing it is missing is silicon. Help carry it from netlist to a die we can measure.
Foundations, research programs, individuals
The design lives in RTL, synthesis, and a bit-accurate simulator — but no one has yet held a StochastiCore chip and measured its real power and timing. Sponsorship pays for the FPGA bring-up and the tapeout that turns simulated numbers into silicon ones.
Sponsor the siliconFabs, shuttle programs, hardware labs
A small multi-project-wafer slot would carry one SC compute unit from netlist to measured die. If you run a shuttle, a fab relationship, or a hardware lab with bring-up benches, a partnership here closes the one gap the project openly admits it has.
Offer a fab or benchCloud providers, FPGA owners, makers
Place-and-route, long L-sweep simulations, and gate-level power runs are the slow loop in this work. FPGA time on real iCE40-class boards, or GPU credits for the bit-accurate model, let us widen the evidence faster — and print the losses as honestly as the wins.
Provide computeRTL engineers, SC researchers, skeptics
Everything is open: the Yosys flow, the LFSR semantics, the peer-revision ledger. Audit the synthesis counts, stress the fault model, or argue the energy numbers — the revision that reversed our own energy claim came from exactly this kind of scrutiny.
Pick up the RTLNo tier is “customer support.” Every lane is a way to put weight behind an open research program — and to be named in the record that carries it, including the parts that go against us.
FPGA bring-up and a shuttle tapeout of one SC compute unit — the measured power and timing the project openly says it does not yet have.
Place-and-route, long L-sweeps, and gate-level power runs on real hardware — widening the evidence so wins and losses are both printed at full size.
Engineer time to harden the RTL, extend the fault and energy models, and keep the peer-revision ledger honest as the design moves toward a die.
The honest fine print, unchanged here: stochastic computing is not a throughput or per-op energy win — useful quality costs 29×–116× longer per operation and our gate-level model puts SC energy 250–970× above binary. Backing buys validation and reach, not a rewrite of physics. See the evidence →
Pledge as an individual, sponsor as an organization, join a crowdfunding round, or offer compute and partnership in kind. Tell us how you'd like to help and the team will write back personally — no portal, no equity ask, just the open program and its next bar: real silicon.
Prefer email? Reach us straight at hello@aiteleresearch.com.